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I just finished a reading a couple of online guides on how to use timer registers with pulse width modulation, so I'm still new to its concept. When I looked in the ATMEGA328 specification sheet, I see this table:

enter image description here

The column that I'm not completely clear on is the "Update of OCR1x at". I circled row 14 as an example. If you're operating in mode 14 (ie. setting WGM 13, 12 and 11 to high), then you'll be in Fast PWM. By setting a value for ICR1, you are effectively setting the TOP value, which will control the period of the pulse waves. And the overflow flag on the timer will be set when the timer reaches the TOP value.

So does "Update of OCR1x at" mean that only when when the pulse wave form has reached the value of BOTTOM (or the end of a period), that's when the value of OCR1x will be passed on to the OCx pins if COMx bits are set?

learningtech
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1 Answers1

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So does "Update of OCR1x at" mean that only when when the pulse wave form has reached the value of BOTTOM (or the end of a period), that's when the value of OCR1x will be passed on to the OCx pins...

Yes, that's what it means. To prevent glitches in the PWM output, you frequently do NOT want the PWM waveform to change immediately the instant you update an OCR1A value, for instance, to change the PWM output on output pin A. So, the PWM value you set is double-buffered and only updates the inner buffer used by the output pins once it finishes its current PWM period and reaches the BOTTOM value again, which would be a counter value of 0 in this case. Now, by allowing a previous PWM period to finish before the hardware reads the latest value from the OCR1A/B register (outer buffer) to its inner buffer (which inner buffer actually determines the pin state), you have a nice, clean, glitch-free PWM transition from one value to the next regardless of when you updated the OCR1A or OCR1B output register.

Gabriel Staples
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