Executing Shell command in Makefile rule

Question

I am trying to run a shell command from Makefile rule section. I'm using basename command to get file name couldn't provide correct file name through $$file . anyone please, help.

for file in `ls *.fof`; \
   do \
   $(eval VIP = `basename $$file .fof`) \
   echo "filename with ext. is $$file"; \
   echo "filename is $(VIP)";\
done

More generally perhaps see also https://stackoverflow.com/questions/10024279/how-to-use-shell-commands-in-makefile — tripleee, Nov 16 '18 at 08:40

score 2 · Accepted Answer · answered Jul 24 '16 at 00:46

While you can get there that way, basename(1) is hardly ever needed.

In the shell, the pattern ${file##*/} removes the directory, and ${file%.*} removes the extension. As built-ins, they're faster than invoking an executable.
In GNU make, you have $(notdir $(basename $(file))). BSD make has similar.

I try to avoid loops in make. To accomplish what you're doing, I might do something like

.SUFFIXES = .fof .T
NAMES=$(wildcard *.fof)

all: $(subst .fof,.T,$(NAMES))

.fof.T: 
        echo "filename with ext. is $^"
        echo "filename is $(notdir $(basename($@)))"

score 0 · Answer 2 · answered Jul 23 '16 at 11:32

I could make it work with small changes:

all:
    for file in `ls *.txt`; \
       do \
       VIP=`basename $$file .txt` ;\
       echo "filename with ext. is $$file"; \
       echo "filename is $$VIP";\
    done

changes in the VIP= line
the last echo uses $$VIP

Executing Shell command in Makefile rule

2 Answers2